A frequency divider is a circuit that receives an input signal having a first frequency (Fin) and generates an output signal having a second frequency (Fout). The relationship of Fin to Fout can be expressed as Fout=Fin/N, where N is an integer. Frequency dividers can be implemented in analog or digital domains and are used in many applications. For example, phase-locked loop (PLL) frequency synthesizers use frequency dividers to convert the output frequency of a voltage-controlled oscillator (or a digitally-controlled oscillator, as the case may be) down to a reference frequency. One example type of frequency divider is called a multi-modulus divider (MMD), which includes an asynchronous cascade of divide-by-2-or-3 (DIV23) cells or stages. A conventional MMD consists of N stages and performs a division between 2N and 2(N+1)−1.
FIG. 1 illustrates a schematic drawing showing a conventional DIV23 circuit 100. Frequency dividers are commonly fabricated with D-type flip-flops (DFFs). As is generally known, a D-type flip-flop is constructed from a gated SR flip-flop with an inverter added between the S (set) and the R (reset) inputs to allow for a single D (data) input. This data input D can be used as the set signal, and the internal inverter is used to generate the complementary reset input. As can be seen in FIG. 1, circuit 100 includes three two-input AND gates (110, 112, and 114) and four DFFs (102, 104, 106, and 108). The inputs to circuit 100 include the input clock signal (clk) and two control signals (modin and r). The divisor value (N) of circuit 100 can be set by the two control signals. The outputs of circuit 100 include the divided clock signal (clkdiv) and modout. As will be appreciated, the divided clock signal clkdiv will have a frequency that is equal to the frequency of the input clock signal clk divided by either two or three, depending on the mode of operation. The modout node of circuit 100 may be coupled to the modin node of a preceding cell within a larger divider circuit that includes a series of DIV23 circuits 100. In other example configurations, depending on the application, the DIV23 circuit 100 may be configured with a master-slave configuration, where a master clock signal is applied to two master latches (DFF 102 and 106), and slave clock signal is applied to two slave latches (DFF 104 and 108). In any case, signal modin or signal r or both can be set to logical 0 (LOW) for the divide-by-2 mode (i.e., Fout=Fin/2). For instance, if control signal modin is LOW, then the output of AND gate 112 will be LOW which in turn will cause the signal passing through DFF 106, AND gate 114, and into port D of DFF 108 to be LOW. In a similar manner, if control signal r is LOW, then the output signal of AND gate 114 will be LOW which in turn will cause the signal passing into port D of DFF 108 to be LOW. In either case, the signal output from port Q of DFF 108 will be a logical 1 (HI). As can further be seen, port Q of DFF 108 connects to one of the inputs of AND gate 110. Thus, if Q of DFF 108 is HI, then circuit 100 will function as though DFFs 106 and 108 are not part of circuit 100, and as if the Q of DFF 104 were directly connected to the D port of DFF 102. On the other hand, if the control signals modin and r are both set to HI, thereby setting circuit 100 to its divide-by-3 mode, then DFFs 106 and 108 are active parts of circuit 100. The truth table summarizing the control logic for circuit 100 is provided in Table 1.
TABLE 1Truth Table for DIV23 Circuit 100modinrDivider Mode002102012113